Dwarkesh PatelWhat will computer chips look like in 2045?
Dwarkesh Patel
AI strain on fabs 0:00
AI has created an unusually sharp jump in chip demand, far beyond normal capacity. That means foundries must make more leading-edge compute by producing more chips and by making each chip do more. Intel says that work is limited by the tools it buys from suppliers, especially ASML’s EUV machines. Without the equipment, the chips cannot be made.
How 14A gets ready 1:32
Intel says 14A has been in development for more than three years and is now close to finalization. The team is locking down the tool set and tuning roughly 2,000 factory steps so the process can run repeatably at high volume. Yield is improved by finding defects with inline metrology and end-of-line electrical tests, then tracing each fail back through cross-sections and other analysis.
Backside power choices 15:01
Backside power moves thick power lines to the back of the wafer, which frees space above the transistors for signal lines. Intel says that makes High-NA useful for its own process, because one pass can print wiring that would otherwise need multiple EUV passes. For 14A, it is still an option in the PDK, and Intel will decide with each customer whether the added value is worth the added complexity.
Foundry learning curve 18:00
Intel says becoming a foundry has meant building a formal PDK process from scratch. It did not have one in the old IDM model, where product teams shared transistor data directly. Customer feedback is shaping the PDK’s quality and maturity, and Intel says 14A will start with that in place. The discussion then broadens to 3D logic, CFETs, heat, and long-term limits on scaling.
Materials and stacking 30:01
Ruthenium is being studied because, at very small pitches, it can beat copper once copper needs a liner to make it stick and conduct. The liner takes space, so an etched material like ruthenium can win in the 20-nanometer range. The same kind of tradeoff shows up in choosing process paths: cobalt led at one point, then copper recovered, and the next choice may shift again. CFET, which stacks transistors on top of each other, is also under study. It raises new problems in etching, filling, and connecting the devices vertically, so the lab uses short-loop test vehicles, simple diodes and capacitors, and even atomic-scale 2D films before anything reaches a phone.
Hybrid bonding runway 45:31
Hybrid bonding keeps shrinking the gap between chips. The speaker says first-level interconnect used to be 130 to 150 micrometers, then 25 micrometers in high-volume Foveros, and now sub-10. A paper at IEEE ECTC showed reliable 0.45 micron pitch, which suggests another order of magnitude in density. The same approach could also lower power and heat in CPU and GPU links.
Tool shortages and scale 48:02
Chip output is limited by the whole supply chain, not only by ASML’s EUV tools. Intel says it must squeeze more from the tools already installed, and that once a process flow is set, it cannot simply swap in another supplier’s tool. For a new node like 14A, the aim is to reuse as much of the 18A toolset as possible, though some new tools are still needed.
Rethinking chip factories 1:03:31
The cost of a High-NA EUV scanner and its equipment is about $400 million, which makes simple cost growth look absurd. That leads to a broader question: whether chipmaking should be redesigned from scratch. The industry is deeply risk-averse, so people keep using old fab methods, but the speaker says that can lock in bad habits.
AI-generated summary. It can be wrong or incomplete - check anything that matters against the original.
